In silicon on insulator (SOI) technology a thin semiconductor layer is formed over an insulating layer, such as silicon oxide, which in turn is formed over a bulk substrate. This insulating layer is often referred to as a buried oxide (BOX) layer or simply as a BOX. For a single BOX SOI wafer the thin semiconductor layer can be divided into active regions by shallow trench isolation (STI) which intersects the BOX and provides total isolation for active device regions formed in the semiconductor layer. Sources and drains of field effect transistors (FETs) are formed, for example, by ion implantation of N-type and P-type dopant material into the thin semiconductor layer and/or by the formation of raised source/drain (RSD) structures. A channel region between a source/drain (S/D) pair can be created so as to underlie a gate structure using, for example, a fin that is defined in the semiconductor layer when a FinFET device is being fabricated.
A strained semiconductor layer can be used to enhance the performance of integrated circuits. Charge carrier mobility enhancement results from a combination of reduced effective carrier mass and reduced phonon scattering. In an n-channel MOS field effect FET with a silicon channel improved performance can be achieved with induced biaxial tensile stress in a silicon layer along both width and length axes of an active area or with uniaxial tensile stress along the length axes. In a p-channel MOSFET improved performance can be achieved with induced uniaxial tensile stress in the silicon layer along the width axis only (transverse tensile stress). The p-channel MOSFET can also show enhanced performance with induced uniaxial compressive stress in the top silicon layer along the length axis only (longitudinal compressive stress). Compressive stress can be provided selectively in a silicon surface layer, for example, by using selective epitaxial SiGe stressors in the source and drain regions of a p-channel MOSFET to induce a desired compressive stress along the length axis (longitudinal). Similarly, tensile strain can be provided, for example, by using selective epitaxial Si:C stressors in the source and drain regions of an n-channel MOSFET.